The present invention generally relates to a Josephson memory circuit which includes Josephson junctions serving as memory cells.
Recently, an integrated circuit which uses a niobium (Nb) Josephson junction has been developed. A logic gate which uses a Josephson element enables high-speed switching operation with low power consumption. Thus, a high-speed processor can be achieved by Josephson junctions. As logic gates are configured to operate at higher speed, a memory circuit is also required to operate at high speed.
Referring to FIG. 1, there is illustrated a conventional Josephson memory circuit which serves as a single memory cell. Data is applied to a write circuit 10 at the same time as a write address is applied thereto. The applied data is held as a current which circulates in a superconducting closed loop 10a including a Josephson junction. The presence and non-presence of the circulating current correspond to data `1`, and `0`, respectively. A read circuit 11 is magnetically coupled to the superconducting closed loop 10a and a read address line 12. The read circuit 11 performs an AND operation on a first state where there is the circulating current and a second state where a read address is being applied to the read address line 12. When the AND logic is satisfied, the read circuit 11 switches its state and reads out data from the write circuit 10. A memory cell array is formed by a large number of memory circuits each having the structure shown in FIG. 1.
A memory cell array as described above is formed on a chip independently or with logic gates of a memory peripheral circuit. In either case, a large number of memory circuits is formed on a chip. In order to take into account dispersion in various parameters with respect to the memory circuits and let the memory circuit operate stably, each of the memory circuits must have a large operating margin.
However, data in the write circuit 10 is read out on the basis of the AND logic by the read circuit 11 as described previously. This is further described with reference to FIG. 2. FIG. 2 is a graph of a threshold characteristic of the read circuit 11. The horizontal axis of the graph represents an input signal current, and the vertical axis thereof represents a bias current passing through a read line 13. A hatched area represents a superconducting state, and an area other than the hatched area represents a finite resistance state. The read circuit 11 switches from the superconducting state to the finite resistance state when the bias current becomes equal to ib in the finite resistance state and an input signal current for the read circuit 11 becomes equal to 2ia in the finite resistance state. The input signal current corresponds to the sum of the circulating current& ia and the read address current ia. That is, the read circuit 11 must discriminate the presence of the input signal current 2ia with the bias current ib applied thereto from other states. It follows that the read circuit 11 has a small operating margin with respect to a fluctuation of the bias current and a fluctuation of each of the circulating current and the read address current. Thus, the read circuit 11 frequently malfunctions.